Semiconductor fabrication and manufacturing technologies continue to advance and allow an increase in the number of integrated circuits on a die and across a wafer. Identical circuits on a wafer or within the same die may have different performance characteristics due to fabrication or manufacturing process variations.
Some of the fabrication or manufacturing process variations can be accounted for by using a corner-based static timing analysis approach. The fabrication processes can be characterized by running test chips, circuits designed to capture the process variations, through process corners. Process corners are typically determined by the fabrication facility in order to maintain an acceptable level of die yield. This allows the fabrication facility a method to control and monitor the fabrication process.
A static timing analysis (STA) tool utilizing the process corner models can determine some of the effects of process variation on the circuits. Each process corner can be analyzed and the impact on circuit performance characterized. However, fabrication technology advances have increased the significance of process variations on circuits such that not all process variations can be accounted for using this approach.
STA tools are typically used in the design of integrated circuits to determine the timing performance thereof. STA tools typically trade off accuracy in the results to reduce the computer run-time necessary to achieve those results. Integrated circuit designers may be familiar in how to use STA tools.
Statistical Static Timing Analyzer (SSTA) tools are a newer timing analysis tool that may be used to analyze an integrated circuit design. A SSTA tool can provide timing performance and better accuracy in the timing results with respect to variations and yield. Instead of being conservative, SSTA tools may provide for more aggressive IC designs with smaller die size, more die per wafer, and lower costs per die. However, integrated circuit designers may be less familiar with SSTA tools. The setup/integration time to implement SSTA tools may be longer, run-time may be longer without computer performance improvements, and the results tend to be more complicated and difficult to analyze.
In order to account for all process variations, the number of simulations would increase dramatically such that run time would increase exponentially. However, not accounting for on chip variation and/or design specific process sensitivity could impact the functionality, integrated circuit size, and performance.